This invention relates to programmable logic array integrated circuit devices, and more particularly to improved circuitry for interfacing between the core programmable logic circuitry of such devices and their input and/or output pins.
Programmable logic array integrated circuit devices are well known as shown, for example, by Pedersen et al. U.S. Pat. No. 5,260,610 and Cliff et al. U.S. Pat. No. 5,260,611. Although other constructions of such devices are known and can be used with this invention, in devices of the general type shown in the above-mentioned Pedersen et al. and Cliff et al. patents a large number of regions of programmable logic are disposed on the device in a two-dimensional array of intersecting "rows" and "columns" of such regions. Each region is programmable to perform any of several logic functions on signals applied to that region. Each row may have several associated "horizontal" conductors for conveying signals to, from, and/or between the regions in the row. Each column may have associated "vertical" conductors for conveying signals from row to row. Programmable connections may be provided for selectively connecting the conductors adjacent to each region to the inputs and outputs of the region, and also for selectively connecting various conductors to one another (e.g., connecting a horizontal conductor to a vertical conductor). Interconnection of regions through the above-mentioned conductors and programmable connections makes it possible for the programmable logic array device to perform much more complicated logic functions than can be performed by the individual regions.
Input and/or output pins (generally referred to for convenience herein as input/output or I/O pins) are provided on these devices to allow external signals to enter the device for processing and to allow logic signals produced by the device to exit from the device and be applied to external circuitry. For example, such input/output pins may be located adjacent each end of each row and adjacent each end of each column. Programmable connectors may be provided for selectively connecting each input/output pin to selected ones of the horizontal conductors of the row that the input/output pin is adjacent to the end of, or to the vertical conductors of the column that the input/output pin is adjacent to the end of.
Advances in integrated circuit fabrication technology have made it possible to produce programmable logic array devices with very large numbers of logic regions. Such devices need large numbers of input/output pins. As the number of logic regions and input/output pins increases, it becomes increasingly important to carefully select the numbers and arrangements of the interconnection conductors and the programmable connections between those conductors, as well as between the conductors and the regions and input/output pins. Complete generality of these interconnection resources (i.e., so that any desired interconnection can be made no matter what other interconnections are made) would lead to exponential growth in the chip area occupied by the interconnection resources as the number of logic regions and input/ output pins increases. Moreover, most of these completely general resources would be unused and therefore wasted in virtually all applications of the device. On the other hand, many applications of the device may require substantial interconnection resources, and because the device is intended to be a general-purpose device, it is extremely important for commercial success that the device be capable of satisfying a very wide range of potential applications, many of the requirements of which cannot be known in advance by the designer of the programmable logic array device.
Considerations such as the foregoing make it essential to provide increasingly sophisticated interconnection resources on programmable logic array devices, including in the area of the interface between the input/output pins and the core programmable logic of the device. For example, external circuit constraints may dictate use of certain input/output pins for particular signals, but optimum use of the core logic may require the ability to switch these signals fairly generally relative to the core logic. Again, complete generality of such input/output-to-core interconnection capability is wasteful, so more sophisticated arrangements of such interconnections are needed to provide a high degree of flexibility without such disadvantages as excessive real estate requirements, undue circuit loading, and large speed penalties.
In view of the foregoing it is an object of this invention to provide improved programmable logic array devices.
It is a more particular object of this invention to provide improved arrangements of interconnections between the input/output pins of programmable logic array devices and the core programmable logic of those devices.